High-Performance Motor Control for Formula Student

A project by TUfast e.V.

Introduction

Electric drivetrains in Formula Student place exceptional demands on precision, reliability, and development speed. Each season, student teams must design, manufacture, and validate a complete race car within roughly one year, leaving little margin for lengthy iteration cycles or hardware redesigns. Within this compressed timeline, the drivetrain stands out as one of the most technically challenging subsystems. It must deliver high torque, fast transient response, and robust safety behavior while fitting into a tightly constrained chassis and operating under strict efficiency and thermal limits.

For the TUfast Racing Team at the Technical University of Munich, the inverter forms the core of the electric powertrain. In the xb026 race car, it controls four permanent‑magnet synchronous motors using field‑oriented control. To meet the system’s real‑time and integration requirements, the team selected a Trenz Electronic module built around a Zynq UltraScale+ MPSoC. The module integrates the MPSoC, 4 GB of DDR4 memory, and all required power supplies on a footprint small enough to mount directly inside the inverter. This compact, high‑performance platform enables TUfast to implement a deterministic, high‑bandwidth motor‑control system that also supports vehicle communication, diagnostics, and safety logic within the tight constraints of Formula Student.

Implementation

The inverter architecture is structured around the heterogeneous computing capabilities of the Zynq UltraScale+ MPSoC. Time‑critical control tasks run in the programmable logic fabric of the FPGA, where they execute deterministically and in parallel. This includes the field‑oriented control loops for all four motors, high‑speed current measurement via SPI, rotor‑position acquisition through EnDat encoders, and the generation of precise PWM signals for the gate drivers. Because these functions are implemented directly in hardware, they operate without jitter and maintain stable torque production even at high switching frequencies. The ability to parallelize these pipelines is essential for a multi‑motor drivetrain, where each motor requires its own tightly timed control loop.

Higher‑level tasks run on the MPSoC’s quad‑core ARM Cortex‑A53 processing system. This layer manages supervisory logic, CAN communication with the vehicle network, parameter handling, and diagnostics. TUfast currently uses a bare‑metal software environment to minimize latency, but the hardware supports a future transition to embedded Linux without requiring changes to the carrier board or system architecture. This flexibility allows the team to scale software complexity as the vehicle evolves.

Model‑based development plays a central role in the workflow. Control algorithms are designed and validated in Simulink, then automatically translated into synthesizable VHDL using HDL Coder. The resulting IP cores integrate directly into the Vivado block design, allowing rapid iteration without manual HDL development. This approach reduces the risk of discrepancies between simulation and hardware behavior and is particularly valuable given the limited on‑track testing time available during the season.

Hardware integration is simplified by the Trenz module’s compact footprint and onboard power‑supply architecture. By consolidating the MPSoC, memory, and regulators into a single module, the design of the custom carrier board becomes more straightforward. TUfast embeds the module directly into the inverter PCB, routing sensor interfaces, power‑stage signals, and communication lines in a clean and serviceable layout. Reference designs provided by Trenz streamline the bring‑up process and allow the engineering team to focus on system‑level functionality rather than low‑level board support.

Impact

In Formula Student, where an entire vehicle must be designed and validated within one season, any reduction in engineering overhead directly increases the team’s ability to refine, test, and optimize the drivetrain. The Trenz Electronic module contributes to this efficiency by consolidating the MPSoC, memory, and power‑supply architecture into a single, well‑supported component. This integration shortens the design cycle, simplifies hardware bring‑up, and allows engineers to focus on system‑level behavior rather than low‑level board‑support tasks.

The MPSoC’s architecture, combining deterministic FPGA execution with flexible high-level CPU control further augments this. The system allows deterministic cycle-accurate FPGA execution where needed, while at the same time allowing software-controlled flexibility, and scalability for supervisory logic, communication, and diagnostics. This pairing creates a control platform that is both precise and adaptable, making the best use of the team’s scarce development resources.

The model‑based workflow further accelerates development. Control algorithms created in Simulink can be validated early in the design process and then automatically translated into synthesizable logic. This predictable path from concept to deployment reduces implementation errors and accelerates iterations—an essential advantage when track time is limited and design decisions must be validated quickly.

Together, these advantages produce a drivetrain control platform that is high‑performance, reliable, and competitive. By reducing development complexity, enabling deterministic real‑time behavior, and supporting fast iteration cycles, the Trenz module strengthens TUfast’s ability to deliver a refined electric powertrain within the strict constraints of the Formula Student season.

Contact:
TUfast e.V.
School of Engineering and Design
Technical University of Munich
Boltzmannstr. 15
85748 Garching b. München
https://tufast-racingteam.de/

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